RIFL is used to communicate with Instruments and RIFL and POD Fixtures. RIFL pins are not intended to be used but are documented below for debugging purposes. Clk and I/O are twisted pair. 48V Power is "soft started" and limited to 4.75A@48V (220W).

RIFL requires a minimum of 8-pins identified as: RTN (Chassis Gnd), 10 Mhz Ref Clock (CLKn, CLKp), +48V DC, 48V RTN, Input (Ip/In ir RXp/RXn), Output (Op/On or TXp/Txn) and 10-pin and 12-pin versions implement USBn/USBp are reseved for future use or double up the +48V and 48V RTN pins.

See Also: Testing and Debugging Cassini RIFL https://roos.com/docs/RBES-9JPQQ7?Open

FIX Block (10 pin)


RIFL 10-pin (FIX block)
G1 - RTN (Chassis Gnd)
G2 - No Connection
G3 - CLKn
G4 - CLKp
G5 - Ip
G6 - In
G7 - Op
G8 - On
G9 - 48RTN
G10 - +48V

RIFL pins are Row G. They connect via 10 pin ribbon cable to a RIFL Carrier.


PinG1 -RTN is red side of RIFL header.





TIM Blocks RIFL Top Boards (12 Pin)

12-Pin RIFL Top/TIM Pogos
48V Power is Soft Started and limited to 4.75A@48V (220W)

TSLOTx-1 --> TXOn
TSLOTx-2 --> TXOp
TSLOTx-3 --> RXIn
TSLOTx-4 --> RXIp
TSLOTx-5 --> USBn RESERVED FUTURE USE
TSLOTx-6 --> USBp RESERVED FUTURE USE
TSLOTx-7 --> CLKn
TSLOTx-8 --> CLKp
TSLOTx-9 --> +48V
TSLOTx-10 -->+48V
TSLOTx-11 --> 48RTN
TSLOTx-12 --> 48RTN


Y000099x RIFL Top Boards (Front/Rear)

12 Pins Pogo Block at top edge of a TIM.
TSLOTx-1 is on Top, TSLOTx-12 --> 48RTN is on bottom.



Example Damaged Pins: Note these are reserved for future use.

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RIFL III - CIRCULAR "LEMO" Connector

Used by the "H" ports on the inside of the Testhead to connect Handler/Prober or GPIB Instruments.

Hx-1 --> 48RTN
Hx-2 -->TXDn
Hx-3 -->TXDp
Hx-4 --> RXDn
Hx-5 --> RXDp
Hx-6 --> CLKn
Hx-7 --> CLKp
Hx-8 --> +48V
Hx-9 --> USBn RESERVED FUTURE USE
Hx-10 --> USBp RESERVED FUTURE USE








RIFL II - Legacy RIFL "RJ45 Style" Connector

Located on the output side of the Handler/Instrument PODs.

Px-1 --> RXp
Px-2 --> RXn
Px-3 --> 48RTN
Px-4 --> TXp
Px-5 --> TXn
Px-6 --> +48V
Px-7 --> CLKp
Px-8 --> CLKn