Why is RI Faster to Market (Time) and Faster to Test (Speed)?
Since the mid 90s, RI's ATE has generally been twice as fast as the status quo for RF centric parts. Given this history, the results of proprietary benchmarks are no surprise to us. While I can't explain why the others are so slow, I do have some ideas of why our ATE is as fast as it is.
- Mark Roos
There is a major architectural difference in how Cassini testplans are defined and executed. Most ATE software is written in a high level language as a set of procedures which is then compiled and executed in order by the PC using the tester hardware. Cassini testplans involve defining the state of the ATE and the device, taking some data and then performing math operations. The Cassini compiler then computes the fastest means to collect the data. By removing duplicate state changes and ordering the sequence to minimize the use of expensive state changes, we have seen 30% reductions in test times. The execution is also different in that the compiler generates a stream of hardware changes which are executed by a FPGA based state machine and not the PC. This removes quite a bit of PC related delays during test execution and frees the PC to perform other tasks.
Datalogging is also handled differently. In most ATE the user adds log requests throughout the testplan causing the execution to pause at each request and write to a file. In Cassini the logging is handled by the math subsystem and is held until the testing is complete. While the part is being binned the log is generated. By doing a single write at a time when testing is not being impacted can have a big impact on test time.
DUT Programming Advantages
RI's ATE have always used a protocol aware approach to handling device serial programming. Because of this, the pattern generators are optimized for short patterns which can be changed based on test results. It appears that this is a big help for parts which are controlled and not just scanned.
DC & Digital Advantages
Cassini's DC instruments are not really power supplies but are power audio amplifiers. With smooth, symmetric responses, low noise and wide bandwidth, they require less bypass capacitance on the load boards and therefore have faster settling times.
And finally, SyRF Core™, our RF measurement engine, uses a direct to baseband IQ conversion instead of DSP at an IF. What this means is that we get RF measurement data with no DSP reducing the amount of data collected, transferred and processed. The data we get with a single sample may require 2000 samples and the associated processing in traditional mixed signal ATE. When we do need DSP on the capture we have implemented the DSP in the FPGA attached to the converter thus doing it in real time as part of the capture.
In summary, there is no rocket science here. Decisions we made twenty years ago on architecture have worked out well and still seem to give the best performance for complex RF devices.