The standard procedure for RI testplan execution while switching different supplies to make disconnections before connections. This prevents two supplies from inadvertently being connected to the same point. This approach is used often when making both high current and leakage measurements on the same pin of a DUT. One must be aware that because of this, voltage will not be present during the switch.
There are some times when a dut cannot endure a loss of voltage. For instance when it has been programmed to a given condition.
It is possible using Pre and Post measure groupings to override the sequence and maintain voltage during the switching.
It is advantageous to review the schematic of the resources to understand the approach. A DB line has three options, Open, ON and OFF. In addition, the static digital measure needs to select a Pin. That is represented in the schematic below and the buttons shown.
A Power VI has the Options Off and ON, A DP has the option VCCX, VCCY and Open. This switching in all three resources can be controlled to insure a make before break function.
For instance a typical order of execution for switching a DB line to a VI line for a leakage current measurement would be:
Initial conditions: DB line is open and the VI line is ON...
1. Set Parametric Measure Value to appropriate Voltage (matching VI voltage)
2. Apply that voltage to the appropriate DB pin
3. Turn off the VI output
4. Wait for the DB measurement to stabilize:
- The DB must discharge any small difference in voltage between the two resources.
- if the current limit is small, it may take some time
6. Turn the VI output back on
7. Disconnect the Parametric Measure from the DB Pin
Here is a measurement panel that executes this approach using the Pre and Post measure groupings.
1. Anything you set in a pre measure group must be undone in a post measure group as the pre and post measure override the compiler.
2. This same approach can be applied to the DP lines
3. If you are trying this measurement and the current read back is equal to the limit. The DB line is limiting, the sequence delay might not be long enough, or the voltages are unequal or the capacitance on the dutboard is too big.