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The RI Digital TIM requires vectors in the RI internal vector format to operate and so patterns in other formats need to be translated. The Digital Translator tool allows the user to translate their Digital Pattern files in various standards or formats into the native RI internal digital vector format and saving that to Guru.



The Input Data Formats supported are WGL (pronounced "wiggle"), ATP (legacy tester format), STIL (pronounced "style") that is an IEEE standard and preferred import format, and CSV (comma separated values) helpful for using common desktop spreadsheet tools or text processing languages (like perl) to output a format. Once translated, the native .CFF (common format file) can also be saved or opened from the file system or Guru. Since design tools often generate .WGL which contains a net map showing the internal structure of the logic gates on the device, our parsing tool inverts the logic to represent what the tester emits. ATP and STIL are already tester centric, in that it includes the patterns that the tester should emit. Obviously, this would be a better format to import. Use the Logic Analyzer to jump to the error result from the scan test and use the Pattern Tool to manipulate the patterns directly. If an external tool, like a spreadsheet or other text manipulation based software is needed, CSV and CFF can be used during the debug process to manipulate the Guru pattern data.

Memory per DPins# Instrument
Vector Depth/pin: 16 million vectors (MV)
Fail: 32 thousand vectors
Scan chains (per pin block): 128 MV X 20 pin, 256 MV X 10 pin, 512 MV X 5 pin

To Translate Vector/Scan File
    1. Choose Apps > Digital Translate to open the application (See Figure 1).
    2. Choose a Input Data Format Type (WGL, ATP, STIL, CSV) and appropriate Options.
    3. Choose File > Open to select a file to translated.
    4. Select a Device Type to update the Pin Settings column and choose the appropriate DevicePins object. Use the Device Connection Editor to create pins and pin groups used for mapping.
    5. In the Signals Select pane, choose the signals to translate, usually all of them.
    6. Choose Settings > Scan settings to select which signal names are assigned to the required pin Types. (See Figure 2)
      Choose the valid idle state value for each of the assigned pins. This is the value the DPins instrument will be set when the tester enters the default idle state and before/after the signals are emitted.
      Choose one of the available hardware mappings to help store the vector/pattern in the instrument memory. Narrow is 5 pins, wide is up to 20 pins (requires Device Control Groups). NOTE: If the pattern spans multiple DPins# instruments, it must be loaded into each instrument separately. If the pattern specifies inversions, check this box to ignore those qualifications.
    7. Choose a scan map ( refer to scan maps below )
    8. Choose File > Translate Selected to perform the translation and save a local .cff before saving to Guru. This may be helpful if you are trying to generate the .cff programmatically.
    9. Choose View > View Converted Pattern to open the pattern in a Logic Analyzer window. (See Using Logic Analyzer)
    10. Choose Guru > Save and enter a Name, Version, Status, Type, Category (Permission) and SystemID attributes associated with the translated pattern. Choose SaveAs to create a RiDigitalPattern object that should be loaded into the Digital TIM and used in a testplan and opened by the Digital Pattern and Logic Analyzer apps.
    11. Follow the steps to "Edit" and "Load" the translated pattern into the TIM as described in Product DocsDigital Scan - Using Logic Analyzer and Vector Translator ( http://roos.com/docs/CRRS-8E4VZ9?Open ) and then implement a Test panel using DPins# instrument's Seq Pattern button. (See the Cassini Reference Guide RI8535 Universal Digital section for details)

Input Data Formats
    WGL - (pronounced "wiggle") "The Waveform Generation Language (WGL) is a data description language supported by Test Systems Strategies Inc. A WGL file uses an ASCII representation of the digital waveform data, so can be edited using any text editor. WGL is also an intermediate file format used by the semiconductor industry for converting digital test patterns from a logic simulator to tester hardware, and back again. Test information is represented in a WGL file using a structured, free form language with small, specialized structural blocks contained within larger, more generalized blocks.  A full discussion of the WGL language and syntax is beyond the scope of this article, but can be found in the TDS Languages Guide, Version 2007.1, published by Test Systems Strategies, Inc. " (source: https://www.marvintest.com/KB/Q200203/Translating-Waveform-Generation-Language-Files-WGL-to-Marvin-Test-Solutions-DIO-File-Format )
    Simple.wglSimple.wgl
    ATP - (legacy tester format) Pattern is tester centric
    STIL - (pronounced "style") Standard Test Interface Language (STIL) provides an interface between digital test generation tools and test equipment. A test description language is defined that: (a) facilitates the transfer of digital test vector data from CAE to ATE environments; (b) specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a DUT; and (c) supports the volume of test vector data generated from structured tests. (See IEEE 1450-1999)
    CSV (comma separated values) helpful for using common desktop spreadsheet tools or text processing languages (like perl) to output a format. CSV options include Add Missing Clock and Pin names on first line. The First line should be Names like: Din0, Din1, Din2, Dout0, Doit1, MainClock, scanStrobe, scanClock, scanDrive, scanExpect, and so on. The next row should represent binary data with ASCII values "1","H" (integer 1) and "0","X","L" (integer 0) to express the pattern. In general, "H" (high) and "L" (low) is associated with a value driven from the device (a DUT output pin), where the "1" and "0" tends to be used to show its a value going into the device, a DUT input pin. So the values underneath the "out" pins one would expect to see H,L (although 1/0 is also acceptable here) but underneath the "in" pins we would see 1,0.

    din0,din1,dout0,dout1,scan_en,scan_clk,scan_sdi,scan_stb,scan_sdo
        0,0,0,0,0,0,0,0,0
        0,0,0,0,1,1,0,1,0
        0,0,0,0,1,1,1,1,0
        0,0,0,0,1,1,1,1,0
        0,0,0,0,1,1,0,1,0
        0,0,0,0,1,1,0,1,0
        0,0,0,0,1,1,1,1,0
        0,0,0,0,1,1,0,1,0
        0,0,0,0,1,1,1,1,0
        0,0,0,0,1,1,1,1,0
        0,0,0,0,1,1,0,1,0


Menu Summary
    File menu loads input data formats and saves translated CFF files from and to the local file system. File > Translate Selected is used to convert the input data format into native CFF.
    Guru menu loads and saves translated patterns to the local Guru or an arbitrary Guru server with Select Guru...
    Settings > Scan Settings assigns pins to signal resources ( Clock, Strobe, Drive, Expect, Aux ) and default set idle vector states for when a signal is not specified in the signal. Compress Vectors can be disabled here to debug/validate issues with vector compression. Do not disable this unless working with RI support.
    Settings > Compress Vectors - Enabled means that vectors are compressed while they are saved to Guru. Disabled will use more memory but may be emitted slightly faster.
    Tools menu allows access to a Translate Intel Hex feature for when that is needed to translate binary information from ASCII text.
    View > View Converted Pattern menu opens the converted pattern with a built-in Logic Analyzer window. This option is disabled until File > Translate Selected is performed.
    Help > About displays the application version.
Figure 1: Digital Vector/Scan Translator App


Figure 2: Scan Settings dialog


Related Documents:
Product Docs
Digital Logic Analyzer User Guidehttp://roos.com/docs/TDOO-8EKJFT?Open
Product Docs
Digital Pattern .CFF Formathttps://roos.com/docs/RBEH-A28UC8?Open
Product Docs
Digital Scan - Using Logic Analyzer and Vector Translatorhttp://roos.com/docs/CRRS-8E4VZ9?Open
Product Docs
Digital TIM or Fixture Digital Module Best Practices - How to Avoid Failure Interfacing Due To Wiring Ringing Effectshttp://roos.com/docs/RBEH-8B2UZ6?Open
Product Docs
Digital TIM Scan Operationhttp://roos.com/docs/TDOO-8BYLEX?Open
Product Docs
Digital TIM Timing Diagramshttp://roos.com/docs/RBEH-8C53RT?Open
Product Docs
Digital TIM Users Guidehttp://roos.com/docs/TDOO-8EKNUM?Open

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