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WTW2010_RoosInstruments_EVM_Final.doc WTW2010_RoosInstruments_EVM_Final.doc

WTW2010_RoosInstruments_EVM_Final.pdf WTW2010_RoosInstruments_EVM_Final.pdf

ABSTRACT - Presented is an ATE test solution that employs an FPGA to supplement DSP requirements and data throughput for fast measurement of EVM. This approach seeks to enhance tester flexibility to support new and emerging test standards and devices. A general description of EVM is provided in addition to an overview of the test module architecture. The role of the FPGA and subsequent DSP architecture is provided to illustrate areas of high-speed processing demand and demonstrate strategies for reduced test time and enhanced data throughput. A case analysis of two different DSP implementations that compute differential EVM on a captured baseband Bluetooth signal are presented. A comparison of their performance illustrates non-ideal hardware and digital impairments both from a signal processing and
deconstruction standpoint, as well as their subsequent EVM results for tester architecture considerations and DSP design edification.

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