RI Title
RI logo

DRAFT: This document is still being modified by the author. Any information here is subject to change.

The DPins instruments found in the RI8535A Universal Digital TIM can be used to perform "scan" tests or emit long vectors as "burst" commands. A "scan" test refers to loading a large digital pattern into the DUT and then matching the output to an expected pattern, thus exercising all or most of the logic gates in the DUT. The test requires a pattern file with carefully crafted collection of patterns that are machine generated based on the DUT's design tools to be imported into Guru for use with the DPins instruments, followed by a debug process where a test engineer must often modify the patterns to match actual test results. "Burst" refers to a vector used for device control that is set up with the Device Control Editor. These are simple vectors that are full register length and can be imported and exported as ".csv" file.



Along with Cassini app and the Test Plan Editor UI, three other Guru applications facilitates this process, including: Digital Vector/Scan Translator, Digital Logic Analyzer and the Digital Pattern tool. This assumes a properly defined Fixture, Device Interface Board (DIB), Device Pins using the Device Connection Editor and Device Control definition made with the Device Control Editor. The DutControl definition usually includes a set of SPI commands that would be needed to put the DUT in a mode where the scan patterns can be used.

IMPORTANT: See Product DocsDigital TIM or Fixture Digital Module Best Practices - How to Avoid Failure Interfacing Due To Wiring Ringing Effects for details on how to prepare the Fixture and DUT Board (DIB) hardware for scan.

To Use Digital Patterns with the DPins Instrument for Scan and/or Burst:
  1. Follow the steps below for Assigning Pins with Device Connection Editor to create Device Pins and DIB definitions with the Device Connection Editor used to map "Type" (clock, Din, Dout, scan data,scan expect,etc..) of the signal being imported to a specific DPins instrument pin (i.e. clk = D1-10). See Device Connection Editor - Device Pins for details. For multisite, the DIB definition is used for mapping DUT pins and site (i.e. "Site 1 clk" = D1-10, "Site 2 clk" = D2-10)
  2. Prepare and Import digital pattern by following the To Translate Vector/Scan File procedure in the Digital Vector Translator User Guide. (See Figure 1-1)
  3. Follow the steps below To Load Scan Patterns into the DPins# Instrument(s). These steps must be performed once per pattern per DPins instrument and MUST NOT be done with a Cassini Virtual Workstation (VM).
  4. Follow the steps below To Use Scan or Burst with Cassini Test Plan Editor to create a Test panel using DPins# instrument's Seq Pattern button. (See the Cassini Reference Guide RI8535 Universal Digital section for details.)
    IMPORTANT: The Tetsplan must also be saved on a physical tester for the automated pattern loading feature to work properly (reference Step 8 below).
  5. Use the Digital Logic Analyzer to confirm pattern import and that the vector names are mapped to the appropriate DPins pins. See Digital Logic Analyzer User Guide for details.
  6. Perform live debug based on the scan pattern results using the Digital Logic Analyzer connected to a tester. (See Digital Logic Analyzer User Guide for details.)
  7. If modifications to the pattern are needed, use the Digital Pattern tool and repeat step 4 to load the updated patterns into the TIM and step 5 to save the new pattern with the Testplan. Any updates to patterns requires that it is manually loaded and then the Testplan must be compiled to update the CID stored in the testplan and then saved to permanently use the latest pattern.
    IMPORTANT: Modifying the pattern with the Digital Pattern tool or the Logic Analyzer will save the updated pattern with a new CID. All testplans that reference that pattern will need to be opened on an actual tester and saved to update the pattern.
  8. Cassini application will automatically load the pattern into the TIM by its ri.sys.CreationId (CID) at compile time if it does not already exist in the TIMs flash memory. This makes the process seamless for when the RI8535A Universal Digital TIM is exchanged or if the Testplan or Test Exec is deployed to any other tester.

Assigning Pins with Device Connection Editor:
The physical pins used to emit the patterns are assigned in 3 different ways. A) Device Pins & DIB definitions, B) Only Device Pins Definition C) Within Pattern File. The pattern is mapped to a name with signal assignments mapped to self defined names. For most applications, the pin assignments are defined with the Device Interface Board (aka DIB, Dut Interface instrument, Tester > Change dib..., and RiDutInterfaceDef object) and Device Pins (aka DUT instrument in the config, Tester > Change Pins... and RiDevicePins object). For rare or trivial cases, the pin assignments can also be made in the pattern file directly and permanently assigned to a designated pin. Follow the appropriate procedure below to implement one of the three methods for mapping pins.

Narrow vs Wide Scan Patterns

Most scan testing can be done with the narrow scan mode (5 pins). If more than the 5 defined signals are needed, then wide scan (20 pins) is required. Wide scan has different limitations and requires more setup than narrow scan, but allows up to the full pin count of the digital TIM to be used in patterns. A limitation of wide scan is that the clock pin must be Pin 20 (the high pin) and if less than 20 pins are used then all of the signals in a pattern need to be in the same Dpins# bank. The steps below cover patterns which fit into a single Dpins set (20 pins), but patterns can also be extended to the full width of the Digital TIM (80 pins) if needed, please contact [email protected] for details.

A-Narrow) To Assign Narrow Pattern Via DUT & Device Pins Definitions: (Preferred - Most Flexible - 5 pin Max)
    1. Choose Apps > Device Connection Editor
    2. Choose Device Tab, then Device Con > Load Device (or New Device)
    3. Choose Device Pins tab, then Device Con > Load Device Pins (or New Device Pins)
    4. Choose the DIB tab, then Device Con > Load DIB (or New DIB)
    5. (Optional) Choose the Fixture tab, then Device Con > Load Fixture (or New Fixture). This step can be skipped in most cases because the DPins instrument typically does not have any Fixture switching/MUX in it's path from the TIM to the DUT.
    6. Choose Device Pins tab, and choose Add from the right mouse button menu from the Device Pins Definition table to add a pin definition. In this case, the pin identifier can be arbitrary in the DevicePins object since it will be mapped with the Dut Interface.
    7. Choose Copy Row from the from the right mouse button menu from the Device Pins Definition table to add an additional pin definition. Repeat this step for all DUT pins.
    8. Device Pin Groups table can be used to assign the Pin Identifier, Signal, and Type. Normally, we recommend using Serial Type > DUT Defined button in Test Plans to assign the type by the pin. A Pin Group definition is required for using the Serial Group button to assign pins in the testplan. Grouping pins is helpful when using the Test Plan Editor UI to build test panels that apply to every pin, like for continuity testing. For Scan tests, this may be helpful for isolating scan pins from normal DUT power and control pins. (note: required for Wide Patterns, see A-Wide below)
    9. Choose the DIB tab, then choose Add from the right mouse button menu from the DIB Definition table to add a pin definition. The pins group is used to the DPins pin to the signal in the RiDigitalPattern object.
      Note: Normal clock pins are defined as pins 5,10,15,20. (see Cassini Reference Guide, DPins# > Pin Setup > Clock Pins button for setting to use Data Stb, Read Stb and Clock Width instrument settings.)
      Note: Wide patterns require clock pin 20, see A-Wide below.
    10. Choose Copy Row from the from the right mouse button menu from the Device Pins Definition table to add an additional pin definition. Repeat this step for all DUT pins.
    11. Choose Device Con > Save All to preserve these changes. (RiDevicePinsDef, RiDeviceInterfaceDef)
    12. Close the Device Connection Editor. The next time the Dut and Dut Interface is loaded into the tester configuration, the DPins# instrument pin names will be labeled as the Device Pins names to improve Testplan readability. Remove either instrument from the configuration to see the DPins name again.
A-Wide) To Use Wide Scan Pattern via Via DUT & Device Pins Definitions: (Scan with >5 pins)
    1. Use Device Connection editor to configure RiDevicePinsDef and RiDibDef objects that are used to map to the WGL file signal names and to create a grouping of the scan pins.
    2. Choose Apps > Device Connection Editor.
    3. Chose Dev Conn > Load Device or New Device. If scan patterns are shared between several unique DUTs (part numbers), then use a generic Device name that would apply to each (i.e. DUT5xx).
    4. Choose DevicePins tab, then either Dev Con > Load Device Pins or New Device Pins.
    5. Choose Add from the right mouse button menu to create an entry in the Device Pins Definition table for each signal used from the WGL file. The Pin Identifier can be any unique string while the Pin Name must match the signal name in the WGL file.
    6. Once the pins are defined, create a new Pin Group that contains the pins used in each pattern by choosing Add from the Device Pins Group table's right mouse button menu.
    7. Choose Dev Conn > Save Device Pins to save the RiDevicePinsDef object.
    8. Now map the device pins to the Universal Digital TIM pins with the DIB (Device Interface Board). Select the DIB tab then choose Dev Conn > Load DIB or New DIB.
    9. In the DIB Resource Pins pane, choose Add from the right mouse button menu for each signal. Select the Pin Identifier/Pin Name and the Resource Name (Dpins1) and the Resource Pin (D1-2).
      Note: Wide patterns REQUIRE clock pin to be assigned to D#-20 and all signals must be in the same D# bank. (note: exception for 80 pins of scan, contact [email protected] for details.)
    10. When finished, choose Dev Conn > Save DIB to save the RiDibDef object.
    11. Close the Device Connection Editor by choosing System > Exit.
    12. Choose Apps > Digital Translate app to convert the WGL file to a wide pattern.
    13. Select the Device Type (set in step 3 above) and the Pins Settings (saved in step 10).
    14. Choose File > Open and select the WGL file to import.
    15. Choose Settings > Scan Settings, select Emit scan Vectors as wide and deselect Compress Vectors item (note: not available in recent versions of Digital Pattern tool). All Scan Pin assignments and Scan idle vector settings are ignored.
    16. From the Signals panel, select the Pin Group for this pattern then choose Guru > Save.

B) To Assign Pins Via ONLY Device Pins Definitions:
    In this case the pin identifier can be arbitrary in the DevicePins object with the signal mapping done from Pin Identifier mapped to the . The main purpose of this approach is to support multiple sites where the DIB has some switching (MUX) and a single resource is reused between paths. Alternatively, use method "A" above and define a Pin Definition for "site 2" with different DPins pins. Prefer using the same DPins instrument to avoid having to load the patterns into both. If scan requires up to 5 pins, then up to 4 devices can be used with one DPins instrument
    1. Choose Apps > Device Connection Editor
    2. Choose Device Tab, then Device Con > Load Device (or New Device)
    3. Choose Device Pins tab, then Device Con > Load Device Pins (or New Device Pins)
    4. Choose Add from the right mouse button menu from the Device Pins Definition table to add a pin definition.
      The Pin Identifier value must match the DPins instrument in the form D#-PP where # matches the number after DPins# in the config and PP is replaced with "1" - "20" (no leading zeros) to match the physical pin that is connected to the DUT (i.e. DPins1 Pin 5 would be "D1-5", DPins4 Pin 20 would be "D4-20"). Pin Name value is intended to match the DUT pin name. The Signal value should match "signal" value in the pattern file. The Type value should match the pin type (i.e. scanExpect, scanDrive, scanStb, scanClock). These are used by the designer to align the signal name in the pattern file with the instrument pin when using the Digital Vector Translator app.
      Note: Normal clk pins are defined as pins 5,10,15,20. (see Cassini Reference Guide, DPins# > Pin Setup > Clock Pins button for setting to use Data Stb, Read Stb and Clock Width instrument settings.)
    5. Choose Copy Row from the from the right mouse button menu from the Device Pins Definition table to add an additional pin definition. Repeat this step for all DUT pins.
    6. (Optional) Also, Device Pin Groups table can be used to assign the Pin Identifier, Signal, and Type. Normally, we recommend using Serial Type > DUT Defined button in Test Plans to assign the type by the pin. A Pin Group definition is required for using the Serial Group button to assign pins in the testplan. Grouping pins is helpful when using the Test Plan Editor UI to build test panels that apply to every pin, like for continuity testing. For Scan tests, this may be helpful for isolating scan pins from normal DUT power and control pins.
C) To Assign Pins via Pattern File:
    This quick and simple solution can be done with any text editor modifying the pattern file before it is imported. This is not recommended because it can be overridden with DUT centric definitions and could lead to confusion when pattern modifications occur during the debug process or later in the DUT's life cycle as yield improves and test time optimization is performed.

    Add below the "signals" section of the pattern file. The name should match the DUT pin logical name and the pin= value should matches the number after DPins# in the config (i.e. DPins1 Pin 5 would be "D1-5", DPins4 Pin 20 would be "D4-20").
    signal,name=P_SCAN_B,pin=D1-6
    signal,name=P_RESET_B,pin=D1-3
    signal,name=P_SCLK,pin=D1-5
    signal,name=P_MOSI,pin=D1-2
    signal,name=P_SEB,pin=D1-1
    signal,name=P_MISO,pin=D1-4
Cassini DPins Instrument > Edit Patterns

Once the patterns are saved to Guru (RiDigitalPattern), the pattern must be pushed to the Digital TIM on actual hardware before being added to Test Plans from the DPins# instrument in the Editor window. Follow the steps below to load the pattern and prepare the tester configuration for use in a Testplan.

IMPORTANT: These steps MUST NOT be performed with a Cassini Virtual Workstation. The feature only works when using actual hardware.

To Load a Pattern in Dpins# Instrument:
  1. Choose Short Cuts and choose the latest <Name> Dev Short Cut to launch the Cassini application. RI recommends always developing with the latest Short Cut.
  2. (Optional) Choose Test > Plans and choose the appropriate Testplan to open it in the Testplan Editor UI. This step can be skipped if a Testplan is not yet available. If a Testplan has been previously saved with File > Save Simulation, then the associated Fixture, Device, DIB, and Device Pins defs are embedded in the Testplan and can be activated in one step by choosing Activate Latest with the Testplan selected from the Test Objects browser (System > Test Objects).
  3. Choose System > Tester to open the Configuration window.
  4. Choose the Dpins# instrument that is routed to the DUT. For example, if Dpins1 is connected through the Fixture & DIB to the DUT, then choose Dpins1.
  5. Choose the Edit Patterns > push button in the configuration pane. The window title displays "Editing Patterns for Dpins#" followed by the amount of memory used and dut def, pin def, dib def that are active in the configuration.
  6. (Optional) If a Testplan saved as Simulation was loaded in step 2, then choose Pattern > Testplan\Dut\Pins\Dib select > Testplan. This activates the Device, DIB and Device Pins according to what was saved in the Testplan. Skip the next 3 steps.
  7. Choose Pattern > Testplan\Dut\Pins\Dib select > Dut to activate a Device and filter the choices for Pins and DIB. This and the next three steps are optional if the pins were assigned directly in the pattern (option C above).
  8. Choose Pattern > Testplan\Dut\Pins\Dib select > Pins to activate a Device Pins definition. If the desired Device Pins definition is not listed, remove the Device from the configuration to see a list of all Device Pins definitions.
  9. Choose Pattern > Testplan\Dut\Pins\Dib select > DIB to activate a Device Interface definition. If the desired Device Interface definition is not listed, remove the Device from the configuration to see a list of all DIB definitions.
  10. (Optional) If a the pattern needs to be associated with a specific site, choose Pattern > Testplan\Dut\Pins\Dib select > Site and enter an integer value for the appropriate site. This is also optional if the DIB performs switching or already has site mapping.
  11. Choose Pattern > add from guru and select the pattern translated by the Digital Vector Translator app. If the Dut, Pins or DIB are not active, a prompt will be displayed asking to continue. Arn error can be displayed if the pattern's signals could not be mapped to the DPins#-# instrument pins.
  12. Choose the pattern in the Pick Pattern File prompt and choose select.
  13. If multiple patterns are available, a Pattern Selector prompt appears with the name of the pattern. If every pattern should be loaded, enter * (asterisk) and choose OK to load them all. Otherwise, for each pattern name, choose OK when the name matches the desired pattern and choose Cancel to not load it. Do not change the name of the pattern to a known state, instead choose Cancel or OK to iterate through the list.
  14. View the imported pattern details by choosing it from the left hand column in the Editing Patterns for DPins... window. The window title displays memory and active DIB/DUT Control used to map to the pin.
  15. All loaded patterns are saved to persistent flash memory that will survive being powered off and will be displayed in the left pane and information about the selected pattern is displayed on the right pane.
  16. If "scan map is full" error is reported in the message window, then consider that there are 12 maps available, each holding 32 states or 64 possible named patterns. Less signals could to loaded (step 13), for instance 'reset' signal may be constant throughout the scan and could be removed and generated via a default value or direct DPins trigger or via a Burst Device Control entry. If the problem persists, try enabling "Emit scan vectors as wide" option in the Digital Vector Scan Translator app to encode it as a "full width pattern" which will require much more flash memory storage, but should be able to handle any depth pattern within the memory constraints; 16 MV per pin or 32 KV fail vectors. (TIM specs available by request)
  17. All opened configuration windows can be safely closed.
  18. Open a testplan and select the newly installed pattern from the Editor window (Tester > View...) using DPins# instrument's Seq Pattern button. (See the Cassini Reference Guide RI8535 Universal Digital section for details)
  19. Save the testplan to allow the pattern to be automatically loaded into any DPins instrument whenever the tesplan is compiled in the future. This is required to support production in the field with an arbitrarily assigned RI8535 Universal Digital TIM.
  20. If modifications to the pattern are needed, use the Digital Pattern tool and repeat steps above to load the updated patterns into the TIM and step 18 to save the new pattern with the Testplan. Any updates to patterns requires that it is manually loaded and then the Testplan must be compiled to update the CID stored in the testplan and then saved to permanently use the latest pattern.
    IMPORTANT: Modifying the pattern with the Digital Pattern tool or the Logic Analyzer will save the updated pattern with a new CID. All testplans that reference that pattern will need to be opened on an actual tester and saved to update the pattern.
  21. Cassini application will automatically load the pattern into the TIM by its ri.sys.CreationId (CID) at compile time if it does not already exist in the TIMs flash memory. This makes the process seamless for when the RI8535A Universal Digital TIM is exchanged or if the Testplan or Test Exec is deployed to any other tester.



Cassini Test Plan Editor

Implement scan tests from the DPins instrument and burst vectors from the Dut instrument with the Device Control def activated in the Tester Configuration and Cassini's Test Plan Editor. Patterns must be loaded into the DPins instrument on an actual tester, a Cassini Virtual Workstation (VM) will not work. Testplans can be edited, but the test panel with a scan pattern will not be able to reflect the latest CID of the pattern file stored in Guru (i.e. after a pattern modification) from a Cassini VM.

To Use Scan or Burst with Cassini Test Plan Editor:
    1. Once the scan pattern is pushed to the DPins instrument (above) or the Burst vector is saved with the Device Control Editor, choose Short Cuts and choose the latest <Name> Dev Short Cut to launch the Cassini application. RI recommends always developing with the latest Short Cut.
    2. Choose Test > Plans and choose the appropriate Testplan to open it in the Testplan Editor UI. Choose Test > Plans > new to create a new Testplan. If a Testplan has been previously saved with File > Save Simulation, then the associated Fixture, Device, DIB, and Device Pins defs are embedded in the Testplan and can be activated by choosing Tester > Load Sim or by choosing Activate Latest with the Testplan selected from the right mouse button menu in the Cassini Test Objects browser (System > Test Objects).
    3. Activate the Device Control definition from the Testplan window's Tester >
    4. Choose Tester > View... to open the Editor window.
    5. For burst, choose the connected DPins# > Serial Data button and enter "burst:" followed by the name assigned on the Burst tab of the Device Control Editor into a Pre/Post Measure group where the sequence matters.
      For scan, first load into the DPins# instrument following the procedure above, then select the Dpins# > Patterns pane and choose SeqPattern button and paste into a Pre/Post Measure group where sequence and order matters. For example, if Dpins1 is connected through the Fixture & DIB to the DUT, then choose Dpins1.
    6. Choose Compile and then choose Run.
      Note: Resolve any compile issues before saving.
    7. Choose File > Save Guru to store the current CID of the pattern in the DPins# instrument with the Testplan. This is the pattern that will be loaded automatically when the Teastplan is run on another tester with a DPins instrument that does not yet have this pattern loaded. Alternatively, choose File > Save Simulation to embed the Device Control def (and other active defs) in with the testplan so that the Tester will be updated when this testplan is loaded and those dependanceis will be included in the Manifest for when Guru Browser Exports or Guru Agent copies.
    8. For scan, the non-zero result of a MEAS > Pattern Fail measurement button output shows the location in the pattern where the first failure occurs, (0 = PASS). Use the Logic Analyzer app to identify the scan error location and modify the expected compare pattern as needed.
      IMPORTANT:
      Modifying the pattern with the Digital Pattern tool or the Logic Analyzer will save the updated pattern with a new CID. All testplans that reference that pattern will need to be opened on an actual tester and saved to update the pattern.


Logic Analyzer App

An imported scan pattern (RiDigitalPattern) can be viewed and edited using the Digital Logic Analyzer app that functions similarly to a traditional Digital Logic Analyzer instrument. Then the Logic Analyzer can display signal timing and can be used to edit and save RiDigitalPattern signals. See Digital Logic Analyzer User Guide for details, while the steps below are specifically designed to help while following the To Use Digital Patterns with the DPins Instrument for Scan or DUT Control procedure above.

To View/Edit Patterns with the Logic Analyzer app:
  1. Choose Logic Analyzer from the Apps menu.
  2. Choose Guru > Open to open the Choose a Digital Pattern For Display dialog. Click on any of the column headers to sort by that column, select the pattern to load and choose OK. Enable "Local Scope" to only display patterns that are on the local Guru (loaded before) or select a system ID (aka Guru ID) from the Show only for system pull down menu to limit the patterns to the selected system. To open from a specific version from the pattern's history, type in the Cid in the Selection field. The Cid can be looked up by selecting the RiTestplan with the Test Objects browser and choosing Objects > Inspect Cff.
  3. The message window displays the loading status and reports any errors or warnings that were encountered during the loading process. Please report any unexpected behavior to [email protected]
  4. If comparing patterns, choose Guru > Add Pattern, select a pattern and choose OK. A Patterns Loaded window appears, allowing the pattern to be moved Up, Down or Removed from the list. Only the top pattern at the top of the Patterns Loaded list is displayed in the Logic Analyzer panes.
  5. Patterns are displayed with the Signal name on the left pane and a graphical representation of the pattern in the right pane. Choose Expand/Compress to change the time scale zoom value and Restore to return to the default.
  6. Choose View > Pattern Select to display a thumbnail of the pattern to jump to locations using a graphical view. Click and drag to select a region of scan vectors to display. Choose Text to change select a specific named chain in the pattern file, hold Shift and click to select a contiguous list of patterns, or hold CTL to select individual patterns. Once a location is selected, choose Set to adjust the pattern pane to that location.
  7. Use View > Signal Display Select to open a dialog to filter the patterns by selecting them and then choosing Hide Selected or Show Selected.
  8. Choose Display > Text in the lower pane to change the graphical view to a text edit based view of the patterns with and editable table showing Vector column with each pin and the value at that location for each pin. Click on any value in a pin column for a pull down list of values. Change the Selection Mode from Vector (row), Signal (column) or Entry (one value) to control what is selected when you click in the text view. The rate pull down allow you to show
  9. Choose Edit > Edit... to open a Edit dialog which allows the user to Cut/Copy/Paste/Edit the Vector, SubPatt or Pattern with a three tabbed clipboard that only works with the Text view of the pattern.
  10. After making any modifications, choose Guru > Save to save any changes to the pattern.
    IMPORTANT: Modifying the pattern with the Digital Pattern tool or the Logic Analyzer will save the updated pattern with a new CID. All testplans that reference that pattern will need to be opened on an actual tester and saved to update the pattern.


Figure 1-1: Digital Vector/Scan Translator


Figure 1-2: Dev Con Editor > Device Pins Example


Figure 1-3: Example Device Pins Group


Figure 1-4: DIB Resource Connection


Figure 2-1: Choose a Digital Pattern For Display





DISPLAYING VECTORS GRAPHICALLY

To fill the Logic Analyzer display, pick from either the top menu bar the "File" or "Guru" pull down menu and then select the "Open" command. A dialog box will appear that allows you to pick from the available vector files to display.

The vector file is loaded and the main Logic Analyzer window displays the vectors in it's graphical format with time on the x axis and each of the vector pins in the Y axis. The users can Expand or Compress the time scale of the view by clicking on the corresponding buttons located below the view.

The message window in the bottom of the display provides feedback to the user of operations being invoked by this application such as loading vectors, etc.

Figure 3: Logic Analyzer


PATTERN SELECT TOOL USAGE ON GRAPHICAL VIEW

The Pattern Select small dialog box ( Thumbnail View ) appears to allow the user another tool to Expand or Compress the time scale of the view by selecting the region of the entire vector memory that is to be displayed. To change the default window display size, click with the mouse in the Pattern Select tool on the region of memory that is the starting point and drag it to the end of the region desired to be displayed. The region will be highlighted in red on the Pattern Select tool and the Logic Analyzer display will be updated with the size of the bottom window scroll bar reflecting the size of the portion of the entire vector being displayed. The "Pattern Select" thumbnail view can be invoked from the "View" pull down menu and selecting "Pattern Select" .

Figure 4: Pattern Select Tool


DISPLAYING VECTORS AS A TABLE

If the user prefers to view the loaded vector data in a table view, select the Display Text in the bottom left below the graphical view to invoke the text display that lists the digital pins along the top X axis and the Vectors or time along the Y axis.

Figure 5: Vector as Table


PATTERN SELECT TOOL USAGE ON TABLE VIEW

The Pattern Select thumbnail view can be used during the Table View as well to allow the user to select where in the region of the entire vector memory that the display is to be focused. To change the focus, click with the mouse in the Pattern Select tool on one the available starting points and click the Set button.

Figure 6: Pattern Select



DISPLAYING MULTIPLE VECTOR SETS

Multiple vectors can be overlaid in the Logic Analyzer tool by selecting the pull down menu option: File (or Guru) and selecting "Add Pattern". A dialog box will appear that allows you to pick from the available vector files to add to the display.

Figure 7: Multiple Pattern Sets



MANAGING MULTIPLE VECTOR SETS

When more than one pattern is overlaid the "Patterns Loaded" dialog is automatically displayed. It can also be displayed at any time by choosing "View Patterns Loaded" from the "View"pull down menu. The Select patterns Dialog is very useful allowing changing of the order of the loaded patterns and adding as well as removing patterns loaded from the Logic Analyzer display.

Figure 8: Multple Vector Sets


SELECTING SIGNALS TO DISPLAY

On larger vector sets, the user may want to limit the number of signals displayed, and this can be accomplished through the use of the "Signals Display" dialog box. This is invoked by selecting the pull down menu "View" and clicking on "Signals Display Select...". The Dialog box lists all the signals defined and allows the user to highlight several signals and then either select them to be Hidden or to only display those selected.

Figure 9: Signals Display



BOUNDARY SCAN REGISTERS

Boundary Scan Registers can be view using the "View" pull down menu selection "SVF Registers..." which opens a "Boundary Scan Viewer" Dialog Box. The registers can be listed as Hex or Binary by selecting them in the "View" pull down menu in the Dialog Box.

Figure 10: Boundary Scan


EDITING VECTORS SETS

Once loaded, vector sets can be edited in the Logic Analyzer by selecting the "EDIT" pull down menu and selecting "Edit..."which brings up the Editing Clipboard. The Dialog box allows for Cut, Copy, Past, and modifying ( Editing) of parts of entire Vectors, Patterns, or Sub Patterns.

Figure 11: Edit Vectors



LOGIC ANALYZER TOOLS

There are several tools that are included in the "Tools" pull down menu that facilitate easy navigation through vector sets and making measurements.

Figure 12: Logic Analyzer Tools Menu



Figure 13: Dpins1 > Edit Patterns > Pattern Menu


Figure 14: Pick Pattern File prompt


Figure 15: Pattern selector? Prompt


Figure 16: DPins1 Patterns > group_ALL Pattern Details


Pattern menu options
add from guru Provides selection which can be added
remove Removes the selected pattern
rename Rename the selected pattern. This name is what is referenced in the test plans
save Writes the pattern directory to the TIM. This is done automatically after each load so it is not necessary
restore Reads the patterns stored in the TIM and updates the list in the left pane. (Automatically done at startup)
test Computes the checksum of the pattern selected and the result is written to the message window.
Used to check for possible corruption of the data once transferred to the TIM.
inspectMaps - These are the serial scan maps.


Pattern Menu picks sub menus



Dut/pins/dib Description
dut Selects a device family.
This is optional and if selected limits other selections to only those for this device
pins Device pins objects have information on the device to hardware mapping.
For use see pin mapping below
dib The dib may also have pin mapping so it may need to be selected as well.



Erase Menu
memory Executes a full erase of the entire memory. Takes about a minute
All patterns Erases just the used portion.
last pattern Erases just the last pattern written

NOTE : Erased files and pattern storage
The memory in the TIM is flash memory so files when files are added they are not actually
removed but overwritten. During development work, it may beneficial to clean up the memory
occasionally, if it gets filled with obsolete objects.

Errors during loading.
The main potential error currently is a warning that the scan map is full.
There are 12 maps available each holding 32 states of 64 possible.
This is enough for most scans. If you get this message, one solution is to select another option when translating. If this does not work then less signals need to be mapped, for instance reset may be constant throughout the scan and could be removed and generated via a default value.
The final solution is to convert to a wide ( full width pattern ) which will require much more flash memory storage, but should be able to handle any depth pattern within the spec. ( 16mb or 32k vectors )

Scan maps
Scan maps store the scan vector in a compressed format that is used natively by the DPins instruments.
They are created on-the-fly as vectors are encountered and stored in the TIM along with the pattern information.
Standard ( reserved names ) are "scan1", "spi", "jtag" and "i2c" and then there are 12 maps available, must be alpha numeric only and must be less than 28 chars.



Figure 16: Cassini Test Plan Editor > Tester > View... > DPins# > Pattern


Figure 17: Example Testpland with Burst Test Panel
Example_Serial_Comm_HighSpeed_Burst.gzp
The test plan is called 'Example_Serial_Comm_HighSpeed_Burst'. The device and device control should activate with the test plan but, if it doesn't, the device is called 'Example_Serial_Comm_HighSpeed'.

Figure 18: Reference Specs for WGL, ATP, STIL (IEEE-1450), STDF, SVF

ATP_spec.pdfieee1450.pdfSerialVectorFormat_SVF_Spec_RevE.pdfSTDF Spec V4 2007.pdfWGL_spec.pdf

PrintEmail Link
https://roos.com/docs/RBEH-C4QNFW
ROOS INSTRUMENTS CONFIDENTIAL AND PROPRIETARY
©2011-2022 Roos Instruments, Inc. All rights reserved.